Semiconductor and electronics processing industries continue to strive for larger production yields while increasing the uniformity of layers deposited on substrates having larger surface areas. These same factors in combination with new materials also provide higher integration of circuits per area of the substrate. As circuit integration increases, the need for greater uniformity and process control regarding layer thickness rises. As a result, various technologies have been developed to deposit layers on substrates in a cost-effective manner, while maintaining control over the characteristics of the layer.
V-NAND, or 3D-NAND, structures used in flash memory applications. V-NAND devices are vertically stacked NAND structures with a large number of cells arranged in blocks. Gate-last wordline formation is currently the mainstream process flow in 3D-NAND manufacturing. Prior to wordline formation, the substrate is a layered oxide stack supported by a memory string. The gap space is filled by tungsten using CVD or ALD. The top/sidewall of the memory stack is also coated with tungsten. The tungsten is removed from the top/sidewall of the stack by etch process (e.g., a reactive-ion etch (RIE) process or radical-based etch process) so that the tungsten exists only inside of the gap space and each tungsten fill is completely separated from other tungsten fills. However, due to the loading effect of the etch process, the separation etch often results in different wordline recess from at the top of the stack than at the bottom. This difference becomes more pronounced with increasing oxide stack layers.
Therefore, there is a need in the art for methods for wordline separation in three-dimensional structured devices.